| 摘要 |
A novel buffer design including a differential driver circuit provides an improved overall performance to a microprocessor by reducing the number of cycles required by the microprocessor to access data from a cache memory during a split cache line access. In one embodiment of the present invention, when a request to access data from a cache memory comes from a microprocessor, during a first cycle, a first sense amplifier coupled to the cache memory senses a first cache line from the cache memory. Then a first input driver circuit coupled to the first sense amplifier receives the sensed first cache line and stores the first cache line in a split buffer. Then the first sense amplifier senses a second cache line from the cache memory. Then a second sense amplifier coupled to the split buffer senses the stored first cache line from the split buffer. During a second cycle, a control logic circuit coupled to the first and second sense amplifiers, compares the sensed first cache line and the second cache line and sends a command signal to the first and second input driver circuits to substantially simultaneously output the first and second cache lines to a cache output bus circuit.
|
