FINFET WITH DUAL SILICON GATE LAYER FOR CHEMICAL MECHANICAL POLISHING PLANARIZATION
摘要
A FinFET-type semiconductor device includes a fin structure (210) on which a relatively thin amorphous silicon layer (420) and then an undoped polysilicon layer (425) is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer (420) act as a stop layer to prevent damage to the fin structure.
申请公布号
WO2004112146(A1)
申请公布日期
2004.12.23
申请号
WO2004US17725
申请日期
2004.06.05
申请人
ADVANCED MICRO DEVICES, INC.;ACHUTHAN, KRISHNASHREE;AHMED, SHIBLY, S.;WANG, HAIHONG;YU, BIN
发明人
ACHUTHAN, KRISHNASHREE;AHMED, SHIBLY, S.;WANG, HAIHONG;YU, BIN