A processor, suitable for embedded applications, is disclosed comprising a processor core and peripheral devices. One of these devices is a memory management unit allowing the designer of an application specific integrated circuit (ASIC) embodying the processor to tailor the interface between the processor and memory devices according to the intented memory configuration of the processor. Also disclosed is a computer-aided method of disigning such a processor, allowing a user to specify at descriptor level a Harvard or von Neuman memory interface between the processor and memory devices.
