发明名称 |
Semiconductor integrated circuit including a test facilitation circuit for functional blocks intellectual properties and automatic insertion method of the same test facilitation circuit |
摘要 |
This invention provides a semiconductor integrated circuit in which test facilitation technology (design for testability) of system on a chip (SOC) constructed of functional blocks or intellectual properties (IPs) is improved. This semiconductor integrated circuit takes out a test result of the functional block out of the SOC through a test result storage circuit which signature-compresses the test result.
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申请公布号 |
US6834368(B2) |
申请公布日期 |
2004.12.21 |
申请号 |
US20010960414 |
申请日期 |
2001.09.24 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
NOZUYAMA YASUYUKI |
分类号 |
G01R31/28;G01R31/3185;G06F17/50;G11C29/02;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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