| 摘要 |
PURPOSE:To make the operation speed of a DRAM increase, by connecting a reference clock signal generating circuit and an address system circuit arranged respectively on the facing short sides of a rectangular chip, by using a reference clock signal wiring of a shorted two-layer wiring structure extending along the long side of the rectangular chip. CONSTITUTION:By using a two-layer wiring structure wherein main component is aluminum, and a first layer wiring 4 and a second layer wiring 6 are shorted, the following are constituted, a row address strobe(RAS) system reference clock signal wiring, a column address strobe(CAS) system reference clock signal wiring and an activation signal wiring, i.e., main reference clock signal wiring. In a DRAM 1, a reference clock signal generating circuit (RAS and/or CAS) and an address system circuit (XAB, YAB) arranged respectively on the facing short sides of a rectangular chip are connected by using a reference clock signal wiring of shorted two-layer wiring structure extending along the long side of the rectangular chip. |
