发明名称 WIRING TAPE FOR MOUNTING SEMICONDUCTOR INTEGRATED CIRCUIT ELEMENT, ITS MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method for reducing an aspect ratio (t/λ') of an opening for forming solder bumps with a simplified method, and to provide a wiring tape and a semiconductor device. SOLUTION: An adhesive layer 21 is formed on one surface of an insulating substrate 11, and an aperture part 12 is formed therein by drilling it at a predetermined position by punching. A copper foil 31 is stuck thereto with a heating roll laminator, and the copper foil 31 is subjected to a patterning processing to form pads 31a and a wiring layer of the one surface of the insulating substrate 11. A film 40 equipped with the pads and an elastic member 71 are placed on a press table 61, and are pressurized with a flat plate press or a roll press. Thus, the copper foil of the pad 31a is deformed to form recesses 31c in the aperture part 12 and ball pads 31 b. The wiring tape 100 for mounting a semiconductor integrated circuit element having the recesses 31c and the ball pads 31b is thus obtained. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004356488(A) 申请公布日期 2004.12.16
申请号 JP20030154190 申请日期 2003.05.30
申请人 TOPPAN PRINTING CO LTD 发明人 NAKAMURA KIYOTOMO;OFUSA TOSHIO;NAGAI SOICHI
分类号 H01L23/12;H01L21/60;(IPC1-7):H01L23/12 主分类号 H01L23/12
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