发明名称 |
Lateral PNP transistor using a latch voltage of NPN transistor |
摘要 |
A lateral PNP transistor having either of the collector or the emitter diffusion layers layered with an n+ type diffusion layer, is shown. The added layer serves to increase the static electricity withstand stress along a transistor discharging path. A low withstand stress contributes to transistor damage at high breakdown voltages. When an n+ diffusion layer is formed within a diffusion layer in a lateral PNP transistor the transistor behaves as a combination of two transistors, PNP and NPN, selectively configured.
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申请公布号 |
US5237198(A) |
申请公布日期 |
1993.08.17 |
申请号 |
US19920860271 |
申请日期 |
1992.04.01 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE, HO-JIN |
分类号 |
H01L27/082;H01L29/735;H03F1/52 |
主分类号 |
H01L27/082 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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