发明名称 METHOD OF FILLING HIGH ASPECT RATIO ISOLATION STRUCTURE WITH POLYSILAZANE BASED MATERIAL IN SILICON INTEGRATED CIRCUITS HAVING AT LEAST ONE P-N JUNCTION OR DISSIMILAR MATERIAL INTERFACE PRIOR TO ISOLATION STRUCTURE BUILDUP
摘要 PURPOSE: A method of filling a high aspect ratio isolation structure with polysilazane based material is provided to enhance the etch speed and the durability by improving a process for filling isolation trenches. CONSTITUTION: A silicon substrate(10) is provided. One or more circuit element having a thermal budget prior to forming the isolation structure is formed. The set of trenches in the silicon substrate is etched. The set of trenches is filled with a spin on trench dielectric material containing silazane. The substrate is heated at a temperature of less than about 450 degrees centigrade. The stress in the trench dielectric material is converted from tensile stress to compressive stress by heating in an ambient containing H2O at a temperature between about 450 degrees centigrade and about 900 degrees centigrade. The substrate is annealed by heating in an ambient containing O2 at a temperature above 800 degrees centigrade. The integrated circuit is completed.
申请公布号 KR20040104398(A) 申请公布日期 2004.12.10
申请号 KR20040036786 申请日期 2004.05.24
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION. 发明人 BELYANSKY, MICHAEL P.;DIVAKARUNI, RAMA;ECONOMIKOS, LAERTIS;JAMMY, RAJARAO;SETTLEMYER, KENNETH T. JR.;SHAFER, PADRAIC C.
分类号 H01L21/76;H01L21/762;H01L21/8242;H01L27/108;(IPC1-7):H01L21/76 主分类号 H01L21/76
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