| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To prevent false lock while reducing layout area and drastically reducing power consumption and to generate a delay clock whose delay time is adjusted with high precision. <P>SOLUTION: A false lock prevention circuit 4 and a delay detection circuit 7 are provided to a DLL circuit 1. The delay detection circuit 7 detects delay time of a delay element provided to a delay circuit 2 and outputs control signals C1, C2 according to its detection result. The false lock prevention circuit 4 controls UP and DOWN pulses which are output of a phase comparator 3 based on the control signals C1, C2 outputted from the delay detection circuit 7. The false lock prevention circuit 4 outputs the output of the phase comparator 3 as it is when it is within a normal lock range, blocks the output of the phase comparator 3 and outputs either of the UP or DOWN pulses to a charge pump 5 when it is not within the normal lock range. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
