发明名称 DATA PROCESSING UNIT AND CONTROL METHOD FOR DATA PROCESSING UNIT
摘要 PROBLEM TO BE SOLVED: To realize high quality service for multimedia information requiring real time performance without being restricted by a capability of a CPU and a memory size or the like. SOLUTION: A CPU 11, a main memory 12, a voice output interface 54, a display interface 56, a voice input interface 58, a video input interface 60, and an asynchronous transfer mode(ATM) communication adaptor 61 provided with a bus controller 62 and with a management table 64 storing in cross reference a virtual path(VP), a virtual channel(VC) and a direct memory access(DMA) transfer address for each interface (data with different attribute) are connected to a system bus 13. Each interface is provided with a memory (54d-60d) possible for DMA transfer from the bus controller 62 and a header delete/addition circuit (54c-60c) for a transfer control protocol and data are transferred directly not via the CPU 11 and the main memory 12 between the ATM communication adaptor 61 and each interface.
申请公布号 JPH1093580(A) 申请公布日期 1998.04.10
申请号 JP19960246731 申请日期 1996.09.18
申请人 HITACHI LTD 发明人 JIKUYA TAKAYUKI;HATA EIZO;KIMOTO MASAHIRO
分类号 G06F13/00;H04L12/28;H04L12/70;H04L29/04;H04N7/10;H04N7/24;H04N19/00;H04N19/42;H04N19/426;H04N21/6371 主分类号 G06F13/00
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