发明名称 |
Semiconductor memory device and bit line sensing method thereof |
摘要 |
In a semiconductor memory device, a circuit for controlling a voltage level applied to a bit line isolation circuit preferably includes a memory cell connected between a cell bit line pair and a word line; a bit line pre-charge circuit; a sense amplifier bit line pre-charge circuit; a charge transfer circuit connected between the cell bit line pair and the sense amplifier bit line pair; a first sense amplifier circuit for amplifying a voltage of the sense amplifier bit line pair to a first voltage in response to a first control signal; and a second sense amplifier circuit for amplifying the voltage of the sense amplifier bit line pair to a second voltage in response to a second control signal. The combination of the two-stage sense amplifier ciruitry allows for the accurate determination of minimally-different logical voltage levels and minimized circuit area.
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申请公布号 |
US6829189(B2) |
申请公布日期 |
2004.12.07 |
申请号 |
US20020290284 |
申请日期 |
2002.11.08 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LIM KYU-NAM;YOO JEI-HWAN;KANG YOUNG-GU;SHIM JAE-YOON |
分类号 |
G11C11/409;G11C7/06;G11C7/12;G11C11/4076;G11C11/4091;(IPC1-7):G11C7/00;G11C7/02;G11C8/00 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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