| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device including a plurality of nonvolatile memories in which the operating speed can be enhanced while reducing the area of the peripheral circuit. SOLUTION: The semiconductor device comprises a plurality of nonvolatile memories 100 arranged in the row direction and the column direction intersecting the row direction. The nonvolatile memory 100 comprises a gate insulation layer 22 provided on the channel region of a semiconductor layer 10, a gate conductive layer 14 provided on the gate insulation layer 22, first conductivity type first and second impurity regions 24 and 34 provided on the semiconductor layer 10 to sandwich the gate conductive layer 14, and a bit conductive layer 80. The bit conductive layer 80 connects the first impurity regions 24 of the nonvolatile memory 100 arranged in i row [j+1] column electrically with the second impurity regions 34 of the nonvolatile memory 100 arranged in [i+1] row [j+1] column. COPYRIGHT: (C)2005,JPO&NCIPI
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