VECTORED FLIP-FLOPS AND LATCHES WITH EMBEDDED OUTPUT-MERGE LOGIC AND SHARED CLOCK DRIVERS

摘要

A logic cell includes a shared clock driver to drive vectored sequential logic elements such as flip-flops and latches with merged outputs. In one embodiment, a logic cell includes a clock signal directly input to the flip-flops, which act as a passgate for latches. The clock signal is also input to a single inverter whose output drives the flip-flops. The outputs of the flip-flops are input into one or more logic gates embedded within the cell. The logic gates generate logical outputs for data signals input to the cell.