| 摘要 |
PROBLEM TO BE SOLVED: To provide a pipeline-type analog/digital converter which simultaneously satisfies requests of high precision and high speed. SOLUTION: An analog input signal AI is kept by a sample holding amplifier (SHA) 12 with a voltage amplification rate 1/2, and is outputted as voltage V12. Voltage V12 is converted into a digital signal of 1.5 bits in sub-analog digital converters (SADC: comparators 13 and 14 and encoder 15). It is converted into an analog signal in sub-digital/analog converts (SDAC: switches 16a to 16c) and is given to SHA18. Voltage V12 and differential voltage of SDAC are doubly amplified and is given to a next analog/digital conversion stage 20 as voltage VA. Thus, an input voltage range of respective SHA is suppressed to 1/2 of that of a conventional case, and a high speed operation is realized without impairing linearity. COPYRIGHT: (C)2005,JPO&NCIPI
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