发明名称 |
Evaluation configuration for semiconductor memories |
摘要 |
An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS evaluation stage from the bipolar evaluation stage. The evaluation configuration can reliably detect very small read signals and allows a high integration density.
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申请公布号 |
US6806550(B2) |
申请公布日期 |
2004.10.19 |
申请号 |
US20020244258 |
申请日期 |
2002.09.16 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
HOFFMANN KURT;KOWARIK OSKAR |
分类号 |
G11C29/00;G11C7/06;G11C11/4091;H01L27/108;(IPC1-7):H01L29/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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