TEST CIRCUIT FOR INPUT-TO OUTPUT SPEED MEASUREMENT

摘要

A test circuit (2) aids in accurately measuring the input pin (29) to output pin (31) signal propagation speed through an integrated circuit by providing a D flip-flop (33) in the signal path near the output pad (31) to register the arrival of a test signal transition. The flip-flop is clocked (CLK; 34, 35) at various clock frequencies. At the high frequencies, test signal transitions applied at the input pad (29) coincident with a clock transition do not arrive at the output pad in time to be registered at the next clock transition (Q; 36, 37 = low). At lower clock frequencies, the test transition has time to propagate through the integrated circuit and thus will be registered (Q; 36, 37 = high) by the flip-flop. By successively lowering the clock frequency and sending test signals through the circuit, one-half of that clock period (1/2 x TCLK) that just registers the test signal transition corresponds to the input-to-output delay time (Tdelay) being measured.