发明名称 FAILURE DETECTION CIRCUIT AND FAILURE DETECTION METHOD
摘要 PROBLEM TO BE SOLVED: To provide a failure detection circuit and a failure detection method capable of easily detecting the failure with a test pattern prepared in a memory BIST circuit. SOLUTION: This circuit is provided with a memory BIST circuit 140 for detecting the failure of a memory macro 100, a combination logic circuit 110 that uses the output signal of the memory macro 100 as the input, BIST input selectors 1,600, 160n inputting an output signal of a logic output holding flip-flop 120 for holding the output signal of the combination logic circuit 110 and the output signals of the memory output holding flip-flops 1,500, 150n for holding the output signal of the memory macro 100 to the memory BIST circuit 140 by selectively changing over them, and a path activation control circuit 130 for controlling so that an input signal of the combination logic circuit 110 is propagated to the logic output flip-flop 120 by a transition of the output signal of the memory macro 100. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004334933(A) 申请公布日期 2004.11.25
申请号 JP20030125740 申请日期 2003.04.30
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ARIGA YOSHITOSHI;OZAKI SHINJI
分类号 G01R31/28;G11C29/00;G11C29/10;G11C29/12;(IPC1-7):G11C29/00 主分类号 G01R31/28
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