| 摘要 |
A clock recovery system includes a signal summer, a signal source, and an analog-to-digital converter (ADC) interposed in a phase locked loop (PLL). The ADC measures a calibration error signal with the signal source providing a stimulus signal to the signal summer, with a data signal applied to a phase detector within the PLL, and with the PLL in a phase locked state. One or more response characteristics of the PLL are determined based on the measured calibration error signal. The one or more response characteristics can be applied to measurements of a measurement error signal acquired by the ADC with the stimulus signal not provided to the signal summer, with the data signal applied to the phase detector, and with the PLL in the phase locked state.
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