发明名称 MEMORY DEVICE CAPABLE OF ADJUSTING BIT LINE SENSING MARGIN TIME FOR TEST MODE, ITS BIT LINE SENSE AMPLIFYING METHOD AND CONTROLLER
摘要 PROBLEM TO BE SOLVED: To provide a bit line sense amplifying method capable of optionally adjusting the sensing margin time of a bit line, and a memory device provided with its function. SOLUTION: This memory device includes a memory cell 350 which can select and adjust the sensing margin time required in a test mode and is connected to a bit line and a word line, means 320, 330, 340, 360 and 380 for loading data stored in the memory cell 350 to the bit line, a bit line amplifying means 390 for amplifying a data signal loaded to the bit line, and a control means 400 for activating the enable signal after the sensing margin time has passed as much as a set delay time in a normal mode, and adjusting the sensing margin time when a prescribed signal is inputted from the outside of a chip to activate the enable signal in a test mode. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004335078(A) 申请公布日期 2004.11.25
申请号 JP20040107874 申请日期 2004.03.31
申请人 HYNIX SEMICONDUCTOR INC 发明人 DEN SHOKO
分类号 G11C29/56;G11C7/06;G11C11/4091;G11C29/14;(IPC1-7):G11C29/00 主分类号 G11C29/56
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