| 摘要 |
<P>PROBLEM TO BE SOLVED: To execute two instructions in parallel at the same clock cycle by the use of only one computing element, and hereby improve a data processing speed. <P>SOLUTION: A main-system instruction for realizing all instruction sets and a subsystem instruction for realizing data transfer between a register part (a data holding means) 103 and a data RAM (a data storage means) 106 are previously stored in a code RAM 100. A decoding part 102 simultaneously decodes two instruction codes of the main-system instruction and the subsystem instruction to direct processing to each constituent element. Thereby, for example, addition processing of two pieces of data held in a prescribed register of the register part and data transfer processing between the register part and the data RAM can be processed in parallel by the main-system instruction. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
