发明名称
摘要 PROBLEM TO BE SOLVED: To provide a binary-decimal conversion circuit which is increased in the processing speed for conversion from a 4-bit binary number to a decimal number. SOLUTION: This circuit has a decimal adder 13 which adds decimal data and has two data inputs and a carry input, a decimal-binary 20-multiple generating circuit 15, and a decimal 4-multiple generating circuit 16, and inputs the output of the decimal 20-multiple generating circuit 15 inputting the output of a decimal data register 14 as an arithmetic result to the high-order part of one input of the decimal adder 13 and the most significant 4 bits of the binary data register 12 holding binary data to be converted to the low-order part of a decimal 20-multiple inputted to one input of the decimal adder 13. Further, data generated by inverting the output of the decimal 4-multiple generating circuit 16 inputting the arithmetic result are inputted to the other input of the decimal adder and 1 is always inputted to the carry input of the decimal adder 13 to generate a complement of 2 to the decimal 4-multiple.
申请公布号 JP3592242(B2) 申请公布日期 2004.11.24
申请号 JP20010020210 申请日期 2001.01.29
申请人 发明人
分类号 G06F5/00;(IPC1-7):G06F5/00 主分类号 G06F5/00
代理机构 代理人
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