发明名称 Exception handling using an exception pipeline in a pipelined processor
摘要 A programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The execution and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.
申请公布号 US6823448(B2) 申请公布日期 2004.11.23
申请号 US20000738081 申请日期 2000.12.15
申请人 INTEL CORPORATION;ANALOG DEVICES, INC. 发明人 ROTH CHARLES P.;SINGH RAVI P.;OVERKAMP GREGORY A.
分类号 G06F9/38;G06F9/48;(IPC1-7):G06F9/00 主分类号 G06F9/38
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