发明名称 |
Method and apparatus for quick clock swapping using much slower asynchronous clock for power savings |
摘要 |
A power reduction device which includes a first clocking device for generating a first clocking signal, a second clocking device for generating a second clocking signal, a synchronizer device for receiving the first and second clocking signals and being responsive to a first select signal and to a second control signal wherein upon receipt of either of the select or control signals, the synchronizing device generating a synchronized signal without a glitch therefrom wherein the synchronized signal corresponding to either the first or second clocking signals. |
申请公布号 |
US6819150(B1) |
申请公布日期 |
2004.11.16 |
申请号 |
US20010957144 |
申请日期 |
2001.09.19 |
申请人 |
SONY CORPORATION;SONY ELECTRONICS INC. |
发明人 |
SANTOSA HANDIONO;KIM SIMON;WANG SHENG HUNG |
分类号 |
G06F1/08;G06F1/32;H03L7/00;H04B1/16;(IPC1-7):H03L7/00 |
主分类号 |
G06F1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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