| 摘要 |
In a method for manufacturing a semiconductor device that includes a memory region and a logic circuit region, the invention provides a dielectric layer that is better planarized upon polishing. The invention provides a semiconductor substrate having a conductive layer that is to become a word gate of the non-volatile semiconductor device, a stopper layer formed above the conductive layer, and sidewall-like control gates formed on both side surfaces of the conductive layer through ONO films above a semiconductor layer in a memory region, and a gate electrode of a dielectric gate field effect transistor formed above the semiconductor layer in a logic circuit region. A dielectric layer is formed over an entire surface of the memory region and the logic circuit region of the semiconductor substrate. A polishing restricting layer is formed above a part of the dielectric layer. The dielectric layer is polished such that the stopper layer within the memory region is exposed, and the gate electrode within the logic circuit region is not exposed.
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