Variable mask field exposure

摘要

A method of fabricating a plurality of integrated circuits on a substrate according to a first integrated circuit design. Each of the integrated circuits is formed with a plurality of layer patterns. At least one first layer pattern of the layer patterns is common with a second integrated circuit design, and at least one second layer pattern of the layer patterns is unique to the first integrated circuit design. The first layer pattern is imaged on the substrate using an exposure tool and a first mask having a first number of the first layer patterns formed in a block thereon. No other layer patterns of the first layer patterns and the second layer patterns are formed on the first mask. The first number is less than the plurality of integrated circuits formed on the substrate. The first layer patterns are imaged on the substrate by exposing and repeating the block of first number of first layer patterns across the substrate with the exposure tool. The first layer patterns on the first mask are formed at a size that is larger than a size at which the first layer patterns are imaged on the substrate. The second layer patterns are imaged on the substrate using an exposure tool and a second mask having a second number of the second layer patterns formed in a block thereon. At least one additional layer pattern of the second layer patterns is formed on the second mask. The second number is less than the plurality of integrated circuits formed on the substrate. The second layer patterns are imaged on the substrate by stepping and repeating the block of second number of second layer patterns across the substrate with the exposure tool. The second layer patterns on the second mask are formed at a size that is larger than a size at which the second layer patterns are imaged on the substrate.