FERROELECTRIC MEMORY DEVICE

摘要

A ferroelectric memory device (101) has memory cells each composed of a memory cell transistor and a memory cell capacitor. Each memory capacitor (101a) is composed of a lower electrode (2) independent from the other lower electrodes, a ferroelectric layer (3) formed on the lower electrode (2), and an upper electrode (4) formed on the ferroelectric layer (3) and connected to other upper electrodes to serve as a plate electrode. The width of the upper electrode is smaller than that of the ferroelectric layer. Since the width of each upper electrode is smaller than that of each ferroelectric layer, current leak between the upper and lower electrodes is prevented. The intervals between the memory cell capacitors can be decreased without causing current leak between the upper and lower electrodes, thereby achieving a smaller memory cell size.