SEMICONDUCTOR MEMORY DEVICE WITH CONTROL CIRCUIT CONTROLLING LOW POWER CONSUMPTION MODE, ESPECIALLY SYNCHRONIZING CHIP SELECTION SIGNAL WITH CLOCK SIGNAL

摘要

PURPOSE: A semiconductor memory device with a control circuit controlling a low power consumption mode is provided to reduce power consumption by blocking a clock signal from being delivered to a portion of internal circuits under a standby mode. CONSTITUTION: A semiconductor device includes a control circuit for controlling internal circuits(20) to operate in a standby mode in response to a chip select signal(CSN). The semiconductor device further includes a first buffer circuit(12), a second buffer circuit(14), and a pulse blocker(16). The first buffer circuit receives the chip select signal. The second buffer circuit receives a clock signal. The pulse blocker blocks the clock signal from being transferred to the internal circuit via the second buffer circuit in response to the chip select signal under the standby mode, thereby reducing power consumption of the internal circuit.