发明名称 METHOD FOR ELECTROPLATING METAL WIRE
摘要 PROBLEM TO BE SOLVED: To provide a method for electroplating low-resistance metal wire for resolving the problem to fabricate the metal wire on large-area substrate through the technology of photolithographing and etching in the prior art, which improves the RC-delay characteristic of circuit on large- area substrate and reducces the number of masks for processing of a structure of gate overlap lightly-doped drain. SOLUTION: This method comprises steps of: forming an oxide layer on the substrate; depositing a first metal seed layer on the oxide layer; electroplating a first metal layer on the first metal seed layer, which has already been patterned; depositing an inter-layer; depositing a second metal seed layer; and electroplating a second metal layer on the second metal seed layer. Thus, the resistance values of a plurality of the metal wires on the substrate are lowered. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004307988(A) 申请公布日期 2004.11.04
申请号 JP20030146366 申请日期 2003.05.23
申请人 IND TECHNOL RES INST 发明人 HUANG CHUN-YAU;CHIN SEICHU;WU YONG-FU;TSAI CHENG-HUNG;CHYAU CHWAN-GWO;CHU FANG-TSUN
分类号 C25D5/02;C25D5/10;C25D5/34;C25D5/54;C25D7/06;H01L21/288;(IPC1-7):C25D5/02 主分类号 C25D5/02
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