| 发明名称 |
COARSE DELAY TUNER CIRCUITS WITH EDGE SUPPRESSORS IN DELAY LOCKED LOOPS |
| 摘要 |
The invention discloses a delay locked loop which includes a coarse delay tuner circuit with edge suppressors suitable for use with delay locked loops (DLLs). The disclosed tuner circuit provides reduced lock time of the DLL circuit. |
| 申请公布号 |
WO2004055988(A3) |
申请公布日期 |
2004.11.04 |
| 申请号 |
WO2003IB05746 |
申请日期 |
2003.12.08 |
| 申请人 |
KONINKL PHILIPS ELECTRONICS NV;PHILIPS CORP;EASWARAN SRI NAVANEETHAKRISHNA |
发明人 |
EASWARAN SRI NAVANEETHAKRISHNA |
| 分类号 |
H03K5/1252;H03L7/081;H03L7/10 |
主分类号 |
H03K5/1252 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
