| 摘要 |
A low standby current power-on reset circuit is described. A first NMOS transistor's drain is coupled to a first PMOS transistor's drain; source coupled to ground line; and gate coupled to a first capacitor coupled to ground line. The first PMOS transistor's source is coupled to power line; gate coupled to second capacitor coupled to ground line; and drain provides a power-on reset indication. A second PMOS transistor's source is coupled to power line; drain is coupled to drain of second NMOS transistor, gates of first PMOS, second PMOS, and second NMOS transistors, and second capacitor. The second NMOS transistor's source is coupled to gate of first NMOS transistor and first capacitor. A discharge circuit is coupled to power line, ground line, and first and second capacitors for discharging the capacitors when a voltage on power line drops below a level determined by the second PMOS transistor's threshold voltage.
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