发明名称 Redundancy control circuit for semiconductor memory, simultaneously applies voltage to some of program elements to program defect address indicating defect position
摘要 <p>The circuit includes a number of program elements in which a defect address (XAD) indicating the position of a defect is programmed by dielectric breakdown upon application of a voltage (SVT). A voltage control part (101,105,106,107) simultaneously applies the voltage (SVT) to some of the program elements that are to be dielectrically broken down corresponding to the defect address. An independent claim is included for a semiconductor memory.</p>
申请公布号 DE102004016323(A1) 申请公布日期 2004.10.28
申请号 DE20041016323 申请日期 2004.03.30
申请人 ELPIDA MEMORY, INC. 发明人 FUJIMA, SHIRO
分类号 G11C29/04;G11C11/401;G11C17/16;G11C17/18;G11C29/00;H01L29/06;(IPC1-7):G11C29/00 主分类号 G11C29/04
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