发明名称 |
VERIFYING METHOD FOR MASK PATTERN, PROGRAM FOR VERIFYING MASK PATTERN AND METHOD FOR MANUFACTURING MASK |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide verifying techniques for a mask pattern to verify a mask pattern by using approximate verification standards corresponding to the structure of a semiconductor integrated circuit to be finally produced. <P>SOLUTION: The method includes steps of: (S01) preparing a design pattern for the mask to be verified; (S02) producing a mask pattern by proximity effect correction; (S03) dividing the pattern edge of the designed pattern; (S04) defining sampling candidate points in the pattern edge of the designed pattern; (S05) dividing the designed pattern into a plurality of regions; (S06) determining the sampling points; and (S07) verifying the mask pattern by judging whether the dimensional error between the design pattern and the resist pattern at the sampling point is within the defined range or not. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
申请公布号 |
JP2004302110(A) |
申请公布日期 |
2004.10.28 |
申请号 |
JP20030094710 |
申请日期 |
2003.03.31 |
申请人 |
NEC ELECTRONICS CORP |
发明人 |
TONAI KEIICHIRO |
分类号 |
G03F1/36;G03F1/68;G03F9/00;H01L21/027 |
主分类号 |
G03F1/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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