发明名称 Semiconductor memory device including MOS transistors each having a floating gate and a control gate
摘要 A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge accumulation layer and a control gate. The second MOS transistor has one end of its current path connected to one end of a current path of the first MOS transistor. The local bit line connects other end of the current paths of the first MOS transistors. The first switch element makes a connection between the local bit lines and the global bit line. The holding circuit is connected to the global bit line and holds data to be written into the memory cells.
申请公布号 US2004212023(A1) 申请公布日期 2004.10.28
申请号 US20040753324 申请日期 2004.01.09
申请人 UMEZAWA AKIRA;HASEGAWA TAKEHIRO 发明人 UMEZAWA AKIRA;HASEGAWA TAKEHIRO
分类号 G11C16/06;G11C16/00;G11C16/02;G11C16/04;G11C16/10;H01L21/8247;H01L27/105;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L31/062;H01L29/76 主分类号 G11C16/06
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