| 摘要 |
The processor uses a scrambling and/or de-scrambling logic device for processing a binary input dataword, having a base cell arrangement with several base cells (U0,...Un-1) connected in series, each with 2 bit inputs and 1 bit output and associated with a respective bit position of the input dataword, together with a controlled multiplexer device (Uc). An Independent claim for a scrambling and/or de-scrambling method for a binary input dataword is also included. |
