SIGNAL TIMING ADJUSTMENT DEVICE, SIGNAL TIMING ADJUSTMENT SYSTEM, AND SIGNAL TIMING ADJUSTMENT VALUE SETTING PROGRAM

摘要

PROBLEM TO BE SOLVED: To continuously adjust a signal timing such as a clock in an integrated circuit without increasing the circuit scale.

SOLUTION: The delay time from input of data to a circuit block CB1 to output thereof is measured based on the timing of fetching data from the circuit block CB1 to a measurement register MR1 and the timing of fetching data from the circuit block CB1 to a data latch DL 2. An LSI tester 2 sets a well voltage adjustment value so as to average each delay time of circuit blocks CB1-CB3. A selector 12 selects a voltage according to the well voltage adjustment value from the voltage generated in an adjusted voltage generation circuit 11. The selected voltage is applied to the well of a CMOS transistor in clock timing adjustment circuits CTA1-CTA3, whereby the delay time of timing of a clock inputted is adjusted.

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