发明名称 |
Method and apparatus for de-skewing a clock using a first and second phase locked loop and a clock tree |
摘要 |
A technique for de-skewing second and third clocks with respect to a first clock includes receiving the first clock and generating a fourth clock from the first and second clocks. A fifth clock and the third clock are generated from the fourth clock, the fifth clock being substantially identical to the third clock. The second clock is then generated from the fifth clock. The fourth clock is generated by a first phase locked loop having the first and second clocks as its inputs and the second clock is generated by a second phase locked loop connected to a clock tree, the second phase locked loop having the fifth clock and the second clock as its inputs.
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申请公布号 |
US6810486(B2) |
申请公布日期 |
2004.10.26 |
申请号 |
US20010818614 |
申请日期 |
2001.03.28 |
申请人 |
INTEL CORPORATION |
发明人 |
FAYNEH EYAL;KNOLL EARNEST |
分类号 |
G06F1/10;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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