发明名称 |
Method for generating a fault signal in a voltage regulator and corresponding control circuitry for a system voltage regulator |
摘要 |
A method for generating a fault signal in a system voltage regulator by a phase signal includes detecting the system voltage and phase signal; comparing the system voltage and phase signal with respective fault levels; and generating a fault signal upon either the system voltage or the phase signal falling below the respective fault level of the fault levels. The fault signal generating method also inhibits generating a fault signal using a drive signal of the system voltage regulator. A diagnostic circuit for a system voltage regulator is also disclosed.
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申请公布号 |
US6803768(B2) |
申请公布日期 |
2004.10.12 |
申请号 |
US20020300662 |
申请日期 |
2002.11.19 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
SERRATONI CLAUDIO;GALLINARI MAURIZIO;MAGGIONI GIAMPIETRO |
分类号 |
H02J7/14;(IPC1-7):G01R31/02;G01R31/00;G01R31/08;G01R31/327 |
主分类号 |
H02J7/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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