发明名称 |
Method of damascene process flow |
摘要 |
A method of integrated circuit fabrication includes first forming at least one via in an insulting layer, and thereafter forming at least one trench-like structure separately. After a via is formed in an insulating layer, a layer of resist material is formed on the surface of the insulting layer and substantially filled the via. This step is followed by patterning at least one trench-like structure on the resist layer, and the trench-like structure is etched to the desired level. In some other embodiments, at least one trench-like structure is formed before at least one via is formed. An integrated circuit is manufactured by the aforementioned methods.
|
申请公布号 |
US2004198035(A1) |
申请公布日期 |
2004.10.07 |
申请号 |
US20030407095 |
申请日期 |
2003.04.03 |
申请人 |
CHEN CHAO-CHENG;LIN KANG-CHENG |
发明人 |
CHEN CHAO-CHENG;LIN KANG-CHENG |
分类号 |
H01L21/332;H01L21/4763;H01L21/768;H01L23/522;H01L23/58;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/332 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|