发明名称 |
Minimization of clock skew and clock phase delay in integrated circuits |
摘要 |
A hierarchal block for an integrated circuit includes a plurality of sequential registers, a plurality of clock cluster buffers, and a plurality of clock pins. The sequential registers are grouped into a plurality of clusters. Each of the clock cluster buffers is associated with a respective one of the clusters such that a clock net connection can be made to a clock gate input of each of the registers in the respective one of the clusters. Each of the clock pins is associated with a respective one of said clock cluster buffers such that a clock net connection can be made between each clock pin and the respective one of the clock cluster buffers.
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申请公布号 |
US2004196081(A1) |
申请公布日期 |
2004.10.07 |
申请号 |
US20030405926 |
申请日期 |
2003.04.01 |
申请人 |
SRINIVASAN SANDEEP;BEREVOESCU PAUL |
发明人 |
SRINIVASAN SANDEEP;BEREVOESCU PAUL |
分类号 |
G06F;G06F1/10;G06F17/50;H03K5/01;H03K5/15;(IPC1-7):H03K5/01 |
主分类号 |
G06F |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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