发明名称 |
Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same |
摘要 |
A layout design system of a semiconductor integrated circuit, comprising: a library information storage unit configured to register a basic via shape list; a technology database storage unit configured to register a list expressing an optimum wire terminating process for each via shape of said basic via shape list registered in said library information storage unit; and a central processing control unit configured to refer to the lists respectively registered in said library information storage unit and said technology database storage unit, select an optimum line processing, and execute a line design.
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申请公布号 |
US2004199892(A1) |
申请公布日期 |
2004.10.07 |
申请号 |
US20040824857 |
申请日期 |
2004.04.14 |
申请人 |
IGARASHI MUTSUNORI;MITSUHASHI TAKASHI |
发明人 |
IGARASHI MUTSUNORI;MITSUHASHI TAKASHI |
分类号 |
G06F17/50;H01L21/82;(IPC1-7):G06F17/50;H01L21/476 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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