| 摘要 |
An integrated circuit or other electronic circuitry is tested by arranging device pins into multiple-pin groups, and permitting the device pins of the group to share a single tester channel of a piece of test equipment. More particularly, a group comprising a plurality of device pins of the electronic circuitry is designated, and assigned to one of a plurality of tester channels in the test equipment. A test may then be performed on the electronic circuitry, via the assigned tester channel, utilizing at least a subset of the device pins in the designated multiple-pin group. Advantageously, the invention allows high pin count integrated circuits to be tested using inexpensive test equipment platforms.
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