A technique for and structres for camouflaging an integrated circuit structure. A layer ofconductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.
申请公布号
WO2004049443(A3)
申请公布日期
2004.10.07
申请号
WO2003US37654
申请日期
2003.11.20
申请人
HRL LABORATORIES, LLC;CHOW, LAP-WAI;CLARK, WILLIAM, M., JR.;HARBISON, GAVIN, J.;BAUKUS, JAMES, P.
发明人
CHOW, LAP-WAI;CLARK, WILLIAM, M., JR.;HARBISON, GAVIN, J.;BAUKUS, JAMES, P.