CIRCUIT FOR GENERATING PHASE COMPARISON SIGNAL, IN WHICH EXTERNAL CLOCK PREVIOUS TO N-1 TH EXTERNAL CLOCK IS DELAY

摘要

PURPOSE: A circuit for generating a phase comparison signal is provided to remove the limit of the least clock period due to a delay period of the shortest output path by delaying a previous external clock. CONSTITUTION: A first frequency divider(411) is used for receiving a clock signal and dividing the clock signal. A second frequency divider(412) is used for receiving and dividing an output signal of the first frequency divider. A third frequency divider(413) is used for receiving and dividing an output signal of the second frequency divider. A first NAND gate(414) is used for performing a NAND operation for the output signal of the second frequency divider and an output signal of the third frequency divider and outputting a result signal as a phase comparison reference signal. A first inverter(415) is used for inverting an output signal of the first NAND gate.