发明名称 |
DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
摘要 |
Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The memory cell is adapted to operate in a first and a second mode of operation. The first mode of operation is a dynamic mode of operation and the second mode of operation is a repressed memory mode of operation.
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申请公布号 |
US2004190342(A1) |
申请公布日期 |
2004.09.30 |
申请号 |
US20040819550 |
申请日期 |
2004.04.07 |
申请人 |
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发明人 |
FORBES LEONARD |
分类号 |
G11C11/404;H01L29/423;H01L29/51;(IPC1-7):G11C11/34;G11C16/04;G11C16/06 |
主分类号 |
G11C11/404 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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