| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a data processing system capable of preventing leakage of data in a storage without using CPU capability by limiting usage of the storage using a transparent mode by a bus master to a particular bus master without control by software. <P>SOLUTION: The bus master 22-i sends a master ID to a transparent control part of the CPU 16 when carrying out access using the transparent mode to an SDRAM 17. In the transparent control part 31, when a stored value of a corresponding register in an access control register group 32 is "1", access to the SDRAM 17 is allowed within an address range set in a corresponding register of an access allowed address range register group 33, and when the stored value of the corresponding register in the access control register group 32 is "0", access to the SDRAM 17 is forbidden. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
