| 摘要 |
PROBLEM TO BE SOLVED: To provide a CMOS logic circuit wherein the design of circuit with a high speed operation and high expendability is attained, the development man-hours of which can considerably be reduced by remarkably decreasing component adjustment man-hours, and the yield of which is enhanced by using the same basic components to reduce the manufacturing cost. SOLUTION: The logic circuit is configured to include: a first inverting section 4a for inversely outputting a first input signal <0>; a second inverting section 4b for inversely outputting the inverse XA<0> of the first input signal; a first output section 4c for applying NAND arithmetic operation to an output of the first inverting section 4a and a second input signal and providing an output; and a second output section 4d for applying NAND arithmetic operation to an output of the second inverting section 4b and the inverse of the second input signal and providing an output, wherein the first output section 4c and the second output section 4d are respectively switched by the second input signal A<1> and the inverse XA<1> of the second input signal. COPYRIGHT: (C)2004,JPO&NCIPI
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