发明名称 Semi-flash A/D converter with minimal comparator count
摘要 This circuit and method provides an analog-to-digital A/D converter with minimal power and minimal integrated circuit area. A circuit and a method for A/D conversion are provided which maintains performance, but which uses fewer comparators than the prior art. This is achieved by a semi-flash analog-to-digital, A/D, converter circuit with minimal comparator count. The design does not use any subtraction or multiplication operation. It utilizes fewer comparators than the prior art semi-flash A/D converters. The prior art designs use 30 comparators for an 8-bit semi-flash A/D converter while this invention uses 8 comparators. This circuit and method does not require any external Sample and Hold, S/H circuits. It is a hybrid between flash A/Ds and successive approximation A/Ds.
申请公布号 US2004189504(A1) 申请公布日期 2004.09.30
申请号 US20030403445 申请日期 2003.03.31
申请人 AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH 发明人 DASGUPTA UDAY
分类号 H03M1/12;H03M1/14;H03M1/36;(IPC1-7):H03M1/12 主分类号 H03M1/12
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