发明名称 Method of forming bit lines and bit line contacts in a memory device
摘要 A method for forming bit lines and bit line contacts in a memory device is provided. A conductive layer is formed over a substrate to cover a plurality of gate structures thereon. A chemical-mechanical polishing operation is performed to polish the conductive layer so that a cap layer of the gate structures is exposed. A portion of the conductive layer is removed so that only the conductive layer between two neighboring gate structures is retained to serve as a bit line contact. A bit line is formed over the substrate such that the bit line and the bit line contact are electrically connected. Because the bit line contact has a smaller dimension compared with a bit line contact formed using the conventional method, the possibility of having a short circuit between a bit line contact and an adjacent bit line is reduced.
申请公布号 US6797564(B1) 申请公布日期 2004.09.28
申请号 US20030605401 申请日期 2003.09.29
申请人 NANYA TECHNOLOGY CORP. 发明人 WU KUO-CHIEN;CHEN YI-NAN
分类号 H01L21/336;H01L21/60;H01L21/76;H01L21/8242;(IPC1-7):H01L21/336 主分类号 H01L21/336
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