| 摘要 |
PROBLEM TO BE SOLVED: To shorten a cycle time in data write/read without any difficult timing design in a semiconductor integrated circuit including the memory cell of a synchronous type SRAM. SOLUTION: This semiconductor integrated circuit is provided with: a memory cell array 1; an address latch circuit 6 for latching an address signal in synchronization with the rise of a latching control signal; a precharge circuit for precharging a bit line when the precharge control signal is at a first level; a sense amplifier 2 for reading data from a designated memory cell when a sense amplifying control signal is at a first or second level; and a control circuit 8 for generating a local clock signal by changing the duty of an applied clock signal, and generating a latch control signal, a precharge control signal and a sense amplification control signal on the basis of the lock clock signal. COPYRIGHT: (C)2004,JPO&NCIPI
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