发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING ELECTRIC POWER REDUCTION MECHANISM
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit with low power consumption at high speed. SOLUTION: The semiconductor integrated circuit includes an arithmetic circuit (EXA) including registers, the registers maintaining their states even in a sleep state. Further, the semiconductor integrated circuit includes: logic gates connected to the registers; and a control circuit connected to the logic gates, each logic gate includes a first conduction type first MOS transistor and a second conduction type second MOS transistor connected in series, and a connecting point between them is used for an output node. The control circuit is connected to either of the MOS transistors, receives a control signal, allows a first current to flow through one source of the MOS transistors depending on a first state of the control signal, and limits a sub threshold current flowing through the one source of the MOS transistors to a value smaller than the first current according to a second state of the control signal. The semiconductor integrated circuit resumes an arithmetic operation stopped halfway when an active state is restored after the sleep state takes place. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004266858(A) 申请公布日期 2004.09.24
申请号 JP20040137030 申请日期 2004.05.06
申请人 RENESAS TECHNOLOGY CORP 发明人 HORIGUCHI SHINJI;UCHIYAMA KUNIO;ITO KIYOO;SAKATA TAKESHI;AOKI MASAKAZU;KAWAHARA TAKAYUKI
分类号 H03K17/30;H03K17/687;H03K19/00;H03K19/0948;(IPC1-7):H03K19/094 主分类号 H03K17/30
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